Generally, in a semiconductor manufacturing process, a desired pattern is etched by using a resist film as a mask formed on a surface of a target object such as a semiconductor wafer (hereinafter referred to as a ┌wafer┘), and then, removing the resist film from the surface of the wafer. Conventionally, the resist film is removed by employing an ashing method, the method including a simultaneous heating of the wafer in a processing chamber and a removal of the resist film using active species such as O radicals generated during a conversion of O2 (oxygen) gas introduced into the processing chamber into a plasma (a plasma ashing method). As mentioned, by performing the etching process and the ashing process successively in the same processing chamber, the time required to transfer the target object to another processing chamber can be saved, thereby reducing the overall processing time.
However, if the etching process is performed by_using, for example, a fluorine containing processing gas, CF polymers (a fluorocarbon-based polymer) may become deposited on an inner wall of the processing chamber. If the ashing process is continued in such a state, the CF polymers deposited on an inner peripheral surface of the processing chamber may redissociate, and an etching stop layer or an insulating film on the wafer may be damaged by F (fluorine).
Therefore, in order to prevent the damages caused by F, a method of carrying out the ashing process in two steps has been conventionally employed. As the first step, the plasma is generated in the processing chamber without applying a bias voltage to the wafer, which will, in turn, remove the CF polymers deposited on the inner peripheral surface and the like of the processing chamber. As the second step, the bias voltage is applied to the wafer, and the resist film on the wafer is removed. Such a process of removing the resist film in two steps is referred to as a ∉Hybrid-Ashing┘. The hybrid-ashing is disclosed in the following Patent Documents 1 to 6:    Patent Document 1: Japanese Patent Laid-open Application No. H11-145111;    Patent Document 2: Japanese Patent Laid-open Application No. 2000-183040;    Patent Document 3: Japanese Patent Laid-open Application No. H6-45292;    Patent Document 4: Japanese Patent Laid-open Application No. H10-209118;    Patent Document 5: Japanese Patent Laid-open Application No. 2001-176859; and    Patent Document 6: Japanese Patent Laid-open Application No. 2003-264170.
However, in the above described hybrid-ashing, the process on the wafer is stopped while the process of removing the CF polymers is performed in the first step, and thus, the overall processing time may be increased. To shorten the processing time, it is preferable that a time required for the first step performing the removal of the CF polymers should be as short as possible. However, the ashing rate is low in the first step, unnecessarily increasing the processing time.